The memory cell array of a cross-point type resistance change memory, which is one of nonvolatile semiconductor memory devices, is formed by arranging, at the intersections of bit lines and word lines, memory cells each including a variable resistance element and a selector connected in series with the variable resistance element. The variable resistance element can be set to a desired resistance value by controlling the voltage value and the application time. The selector is a rectifying element for preventing disturbance on the peripheral circuits. Both the variable resistance element and the selector are simple 2-terminal elements and can easily be stacked. For this reason, forming a three-dimensional structure of stacked variable resistance elements and selectors makes it possible to implement cost reduction and capacity increase of the resistance change memory.
One of the challenges to commercialization of the cross-point type resistance change memory is to optimize the set current and the reset current of the variable resistance element. An operation of making the variable resistance element transit from a high resistance state to a low resistance state will be referred to as set, and the current and voltage at the time of set will be referred to as a set current and a set voltage, respectively. An operation of making the variable resistance element transit from a low resistance state to a high resistance state will be referred to as reset, and the current and voltage at the time of reset will be referred to as a reset current and a reset voltage, respectively.
If the set current and the reset current are excessive, a large potential difference may be generated across the memory cell array due to voltage drop caused by the micropatterned wiring resistance. To suppress the voltage drop caused by the wiring resistance, the currents need to be reduced. However, if the set current and the reset current are reduced so as to be equal to or lower than the level of thermal noise or noise of circuit components of the semiconductor chip, current detection in the peripheral circuit elements is difficult. That is, the set current and the reset current of the variable resistance element have practical upper and lower limits. It is therefore necessary to make the set current and the reset current fall within the range that satisfies the conditions.
In an actual memory operation, an enormous quantity of data needs to be stored at a high speed. This requires a batch operation of a plurality of memory cells. When the batch operation of memory cells on one interconnection, that is, a so-called page operation is performed, all currents of the plurality of memory cells concentrate to the interconnection. To suppress the voltage drop caused by the interconnection, the set current and the reset current are preferably as small as possible. However, as described above, the set current and the reset current have lower limits. Hence, the number of memory cells of the batch operation is limited. For this reason, the data storage speed decreases.